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High performance logic systems for less power

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February 28, 2013

Non-volatile bistable memory circuits being developed at Tokyo Tech pave the way for highly energy-efficient CMOS logic systems 

Developments in low power, high performance CMOS logic technology are vital to the future of microprocessors and system-on-chip (SoC) devices for personal computers, servers, and mobile/smart phones. Much of the processing in these computing systems is carried out using a volatile hierarchical memory system in which bistable circuits such as static random access memory (SRAM) and flip-flop (FF) play an essential role for fast data-access. However, the power to these bistable circuits cannot be switched off without losing their data. This inability to turn off power is a fundamental problem for energy consumption in CMOS logic systems.

The method for saving energy in CMOS logic systems, called power-gating, uses architecture to cut the supply voltage to idle circuit domains, effectively putting them to power shut-off state to avoid leakage and thereby save static energy. Satoshi Sugahara and his team at the Tokyo Institute of Technology have proposed a new architecture of power-gating using non-volatile SRAM (NV-SRAM) and non-volatile FF (NV-FF) circuits, called non-volatile power-gating, so that the size of logic circuit domains for power-gating is optimally designed, supply voltages to the domains are cut at the optimum times, and the energy cost of the logic circuits is worthwhile.

Over the past few years, Sugahara and his team have been developing non-volatile bistable memory circuits (NV-SRAM and NV-FF) required to establish non-volatile power-gating systems with better overall performance and energy efficiency than conventional power-gating systems1-8. In particular, the researchers have built pseudo-spin metal–oxide–semiconductor field-effect transistors (PS-MOSFETs) for use in the non-volatile bistable memory circuits.

The PS-MOSFET can be configured with an ordinary MOSFET coupled with a spin-transfer torque magnetic tunnel junction (STT-MTJ), and it can reproduce the functions of spin-transistors – in which different electrons spin states or magnetization configurations of the ferromagnetic electrodes are used to control transistor output1. Spin transistors can also store non-volatile information1. In a typical bistable memory circuit, an inverter loop consisting of cross-coupling two CMOS gates is used to store each memory bit. In the new non-volatile bistable circuits, PS-MOSFETs are added to the inverter loop.

Previous attempts to build non-volatile bistable circuits with STT-MTJs have resulted in performance degradation, because the STT-MTJs interfere with their fundamental circuits of the inverter loops. To overcome this problem, the team designed NV-SRAM and NV-FF circuits using PS-MOSFETs. In these circuits, the STT-MTJs can be electrically separated from the inverter loops by the PS-MOSFETs and thus have no degradation effects on the bistable circuit performance.

The NV-SRAM and NV-FF circuits built by Sugahara’s team have performed well under tests so far, compared to conventional SRAM/FF circuits. They also developed architectures for minimizing break-even time (that is an important performance index of power-gating) of the NV-SRAM and NV-FF circuits, including a ‘store-free’ shutdown, wherein existing data is not rewritten, thereby dramatically saving energy.

These new transistor and circuit designs could be pivotal in the development of faster, more energy-efficient processing in future CMOS logic systems. Most importantly, as the researchers state in a recent publication2-5, “Proposed architectures have excellent compatibility with present microprocessor/SoC technologies”, and “Proposed non-volatile bistable circuits using PS-MOSFETs can dramatically reduce the energy issues caused by static power dissipation in advanced CMOS logic systems”

Reference:
1. S. Sugahara, and J. Nitta, Proceedings of the IEEE, “Spin-Transistor Electronics: An Overview and Outlook”, vol.98, no. 12, 2010, pp. 2124-2154.

2. Y. Shuto, S. Yamamoto, H. Sukegawa, Z.C. Wen, R. Nakane, S. Mitani, M. Tanaka, K. Inomata, and S. Sugahra, “Design and performance of pseudo-spin-MOSFETs using nano-CMOS devices”, 2012 IEEE International Electron Devices Meeting (IEDM2012), December 10-12, 2012, San Francisco, CA, USA, paper 29.6.

3. S. Yamamoto, Y. Shuto, and S. Sugahara, "Nonvolatile flip-flop using pseudo-spin-transistor architecture and its power-gating applications", 2012 IEEE Intl. Semiconductor Conference Dresden-Grenoble (ISCDG), September 24-26 2012, Grenoble, France.

4. Y. Shuto, S. Yamamoto, and S. Sugahara, “Analysis of static noise margin and power-gating efficiency of a new nonvolatile SRAM cell using pseudo-spin-MOSFETs”, 2012 IEEE Silicon Nanotechnology Workshop (SNW2012), June 10-11, 2012, Honolulu, HI, USA, paper 4-3.

5. Y. Shuto, S. Yamamoto, and S. Sugahara, “Static noise margin and power-gating efficiency of a new nonvolatile SRAM cell based on pseudo-spin-transistor architecture”, 4th IEEE Int. Memory Technology Workshop (IMW2012), May 20-23, 2012, Milano, Italy, paper 16.

6. Y. Shuto, S. Yamamoto, and S. Sugahara, “Evaluation and control of break-even time of nonvolatile SRAM based on spin-transistor architecture with spin-transfer-torque MTJs”, Jpn. J. Appl. Phys., vol.51, no. 4, 2012, pp. 040212/1-3.

7. S. Yamamoto, Y. Shuto, and S. Sugahara, “Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems”, IET Electronics Letters, vol. 47, no. 18, pp. 1027-1029, Sept. 2011.

8. H. Dyball, “A new spin on the MOSFET”, IET Electronics Letters, vol. 47, no. 18, p. 1007, Sept. 2011.

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Fig. 1 (a) Circuit configuration of PS-MOSFET, in which the STT-MTJ connected to the source of the MOSFET feeds back its voltage drop to the gate, and the degree of negative feedback depends on the resistance state of the STT-MTJ.(b) Simulated output characteristics and current-induced magnetization swiching (CIMS) behavior of the PS-MOSFET.    

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Fig. 2 (a) Circuit configuration of our proposed NV-SRAM cell, in which two PS-MOSFETs are connected to the storage nodes of a standard SRAM cell. (b) Proposed positive edge triggered non-volatile delay-FF (NV-DFF) that consists of a conventional latch (LAT) and a non-volatile LAT (NV-LAT). The NV-LAT and NV-FF can also be configured by connecting PS-MOSFETs in the same manner as the NV-SRAM cell.

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Fig. 3 Schematic of nonvolatile power-gating processor/SoC using NV-SRAM and NV-FF. In the system, logic circuits on a chip are partitioned into several circuitry domains, called power domains that are electrically separated from power-supply lines and/or ground lines by sleep transistors. These domains can be shut down during standby mode without losing their data, and thereby highly energy-efficient power-gating can be achieved, i.e., the static power is considerably reduced even during system run-time.

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