Three Tokyo Tech Faculty Members to Receive 2023 IEEE Fellow Titles

I am honored to receive the title of Fellow from the IEEE. This is an international recognition of the series of research efforts and results, including proposals for research fields, research and development of technologies, and real-world implementation and deployment efforts of the robot audition research that I have been engaged in for many years.

Robot audition is a research area that I proposed with Prof. Hiroshi G. Okuno (Professor Emeritus, Kyoto University, now at Waseda University) under the slogan "Creating 'robot ear' functionality" in 2000, as a research topic originating in Japan. Since a robot's ears receive a mixture of various sounds, the ability to distinguish between sounds is essential. To achieve this functionality, we have continued to lead the world in research, focusing on binaural processing that mimics humans and other living organisms, microphone array processing using multiple microphones, and machine learning-based processing as exemplified by deep learning.

In 2008, HARK (Honda Research Institute Japan Audition for Robots with Kyoto University), an open-source software package of robot audition technology, was released to the public and has remained available to this day, with annual updates and hands-on tutorials for the public. Currently, HARK is being used as a starting point for other developments such as search-and-rescue robots, bird song analysis technology, and communication support systems for the hearing difficulties. The term Robot Audition was also recognized by the IEEE Robotic and Automation Society in 2014 as an official keyword to describe the research field.

This achievement would not have been possible without the help of all of you who have provided guidance and support. I would like to take this opportunity to express my deepest gratitude to my former employer, Honda Research Institute Japan, as well as to the professors and students at universities in Japan and abroad who have conducted joint research with us, and to the students and staff at the Nakadai Laboratory, including alumni and former students.

I am very honored to receive the title of Fellow from the IEEE. This is an international recognition of my research on millimeter-wave wireless communication circuits design, which I have been working on for many years.

Wireless terminals such as smart phones have been communicating using radio waves known as microwaves, but the 5th generation mobile communication system (5G) now uses millimeter waves in addition to microwaves. High-speed wireless communication requires wide frequency bandwidth, but microwaves have already been allocated to various wireless communication systems, making it challenging to achieve higher speeds. Millimeter waves are a type of radio wave, but their frequency is at least 10 times higher than that of conventional microwaves, and a wide bandwidth can be allocated, enabling extremely high-speed communications.

Millimeter wave wireless communications have just begun to be used in 5G, but as an indispensable technology for supporting societal infrastructure, it promises to continue gaining momentum and sophistication. Currently, we are pushing for research and development for practical use with companies, with a view to future 6G and satellite communications. The research results recognized in the selection process for this fellowship could not have been achieved alone. I would like to express my deepest gratitude to all of my collaborators and students.

I am very honored to receive the prestigious title of IEEE Fellow from the IEEE.

I spent much of the 1990s at an electronics company researching CMOS devices and their circuit proofs. At that time, Intel was leading the global semiconductor industry, and research and development was all about increasing speed. I focused on low power consumption from early on and proposed low power consumption not only in terms of static characteristics of devices but also in terms of circuits.

Power consumption is represented by fCV2 (f: frequency, C: capacitance, V: supply voltage). Focusing on the reduction of parasitic capacitance and supply voltage, I devised a new device structure in which impurity ions in the semiconductor are localized in a self-aligned manner, and demonstrated its effectiveness by fabricating a simple CMOS test circuit. Papers summarizing these results have been accepted six times in total, including four consecutive years at the IEEE IEDM (International Electron Devices Meeting), the world's most prestigious international society in the field of electronic devices. In addition, I have adhered to the core principle of low power consumption in academic committee activities and in the commercialization of my proposals. The awarding of the Fellowship is in recognition of this series of accomplishments.

I set off for a new post at Tokyo Tech five years ago. I think I was also recognized for my subsequent participation in research aimed at achieving low power consumption.

I would like to express my deepest gratitude to my senior researchers who have guided me in my research, all the people associated with Tokyo Tech, and my family for their support.